1. Field of the Invention
The present invention relates to a decoder which decodes code data produced by compressing audio/video signals (A/V signals). In particular, the present invention relates to an MPEG decoder which detects and extracts MPEG-coded user data included in video code data.
2. Description of the Related Art
MPEG-compressed video data is processed during decoding in six hierarchical layers: sequence layer, GOP (Group Of Picture) layer, picture layer, slice layer, macro block layer, and block layer. User data, composed of a sequence header, one or more GOPs, and a sequence end code, is added to video data; it is added to video data as necessary in the sequence layer, GOP layer, and picture layer. User data may be used to add superimposed dialogs or scene-searching information to the video code. During decoding, the CPU reads user data to display superimposed dialogs or to search for a scene. In each layer, video data and user data begin with 4-byte code areas each containing a unique start code. During decoding, this start code is used to identify a data hierarchy and a user data area.
A conventional decoder for decoding audio/video compressed code data is shown in FIG. 9. The decoder 1 of FIG. 9 comprises a stream interface 2, an audio/video separator (hereafter called an A/V separator 3), a memory interface 4, an audio decoder 5, and a video decoder 6. The video decoder 6 has a start code detector 15 which, in turn, a user data start address register 16.
The stream interface 2 receives code data (DATA), and outputs data signals (DATAxe2x80x2) to the A/V separator 3. The A/V separator 3 outputs two types of data signals, A_DATA and V_DATA, to the memory interface 4. The memory interface 4 outputs a data signal A_DATAxe2x80x2 to the audio decoder 5, and a data signal V_DATAxe2x80x2 to the video decoder 6. The audio decoder 5 outputs a data request signal A_REQ to the memory interface. The video decoder 6 outputs a data request signal V_REQ to the memory interface. The start code detector 15 outputs a user data detection signal SCD_DET to a CPU 9. The CPU 9 outputs an address signal REG_ADD and a read request signal REG_READ to the MPEG decoder 1, and the MPEG decoder 1 outputs a data signal OUT_DATA to the CPU 9. The following describes the operation.
Code data (DATA) that is input to the MPEG decoder 1 conforms to the MPEG standard. This data is composed of two types of data: compressed audio code data and compressed video code data. These two types of data, each with an appropriate length, are switched as necessary. Upon receiving this code data (DATA), the stream interface 2 synchronizes it with the internal clock signal and sends the data signal (DATAxe2x80x2) to the A/V separator 3. The A/V separator 3 separates the data signal DATAxe2x80x2 into two types of code dataxe2x80x94audio code data and video code dataxe2x80x94and outputs them to the memory interface 4 as two separate data signals, one as A_DATA and the other as V_DATA. The memory interface 4 stores in memory the audio code data (A_DATA) and the video code data (V_DATA ). When decoding, the audio decoder 5 sets the data request signals A_REQ high, and the video decoder 6 sets V_REQ high, as necessary (When these decoders do not request data, A_REQ and V_REQ remain low.) When A_REQ goes high, the memory interface 4 outputs the audio code data to the audio decoder 5 via the data signal line A_DATAxe2x80x2; when V_REQ goes high, the memory interface 4 outputs the video code data to the video decoder 6 via the data signal line V_DATAxe2x80x2.
The video decoder 6 causes the start code detector 15 to detect a start code contained in the video code data received via the data signal line V_DATAxe2x80x2. When the start code detector 15 detects the start code of data of a layer, the video decoder 6 performs decoding processing corresponding to that layer. When the video decoder 6 detects the start code of user data, the video decoder 6 stores the start byte address of the user data into the user data start address register 16 and sets the user data detection signal SCD_DET high (SCD_DET remains low when user data is not detected).
The CPU 9 reads data stored in the memory interface 4 via a register whose address is different from that of the user data start address register 16. When the CPU 9 reads data from the MPEG decoder 1, it sets the read request signal REG_READ low and specifies an address via the address signal REG_ADD. This allows data stored in each register to be read via the data signal line OUT_DATA (When the CPU 9 does not read data, REG_READ remains high.) When the user data detection flag SCD_DET is high, the CPU 9 reads the address from the user data start address register 16 and extracts user data, beginning with the address in the memory interface specified by the user data start address register 16, until the next start code is detected.
One of the problems with the conventional method is that the next code data is input into the memory interface 4 before the CPU 9 completes the extraction of user data from the MPEG decoder 1. This prevents the CPU 9 from extracting the user data correctly.
Code data is input to the MPEG decoder 1 independently of the memory data read operation executed by the CPU 9. That is, code data is written into memory interface 4 whenever there is a free memory area. When the video decoder 6 decodes code data, the decode operation executed by the video decoder 6 involves a decoding delay. Therefore, while the code data is decoded, the address used by the A/V separator 3 to write data into the memory interface 4 via V_DATA is also used, in most cases, by the video decoder 6 to read data from the memory interface 4. However, when the video decoder 6 decodes user data, no decoding delay is generated because the video decoder 6 does not decode the user data but skips it and keeps on reading code data from the memory interface 4 until the start code of the next video data to be decoded is detected. This generates a free area in the memory into which the next data is read before the CPU 9 reads the user data, sometimes preventing the CPU 9 from reading the user data correctly. That is, the above problem depends, to some extent, on the data read speed of the CPU 9; the problem is generated when the speed at which data is read by the CPU 9 via the data signal OUT_DATA is slower than the speed at which data (DATA) is input to the stream interface 2.
To avoid the above problem, the CPU must read user data more quickly. For the CPU to read data more quickly, it is necessary to reduce the cycle time between the time the MPEG decoder 1 detects that the CPU 9 sets the read request signal REG_READ low and the time data is output from memory to the data signal line OUT_DATA. This requires that the MPEG decoder 1 output data to CPU 9 more quickly or that the MPEG decoder 1 be re-designed to suit the data read speed of the CPU 9.
However, an increase in the speed at which data is output from the MPEG decoder 1 to the CPU 9 results in an increase in the LSI size, increasing the production cost. On the other hand, the need to prepare the MPEG decoder 1 specifically designed for the data read speed of the CPU 9 requires many types of MPEG decoders, increasing the development cost.
It is an object of the present invention to provide a decoding method and a decoder which allow the CPU to extract user data from the decoder at any data read speed of the CPU. To achieve the above object, A decoding method of the present invention for decoding audio/video compressed code data, said video code data containing a first code indicating a type of data, said decoding method comprising the steps of: (a) receiving the code data; (b) separating the code data into the audio code data and the video code data; (c) checking if the code data is the video code data; (d) executing processing according to said first code contained in the video code data; and (e) decoding the code data and outputting the decoded code data. MPEG decoding method according to the present invention is a decoding method for decoding MPEG-compressed code data, the code data composed of audio code data and video code data, the video code composed of hierarchical data and user data each preceded by a first start code, wherein a user data start address register is provided to store the start address of the user data, the decoding method comprising the steps of: (a) receiving the code data; (b) separating the code data into the audio code data and the video code data; (c) checking if the code data is the video code data; (d) if the code data is the video code data, if the code data is the video data, and if the user data is detected in the video data, storing an address of the start byte of the user data into the user data start address register and storing the address of a start byte of the user data into the user data start address register; and turning a signal on, the signal indicating that the user data was detected; and (e) decoding the code data and outputting the decoded code data.
According to the present invention, the CPU receives, before code data entered into the decoder is decoded, a user data detection signal indicating that the code data contains user data. Upon receiving this signal, the CPU turns on the read request signal, with the address of the user data start address register specified, to read the address from that register. The CPU then reads data, beginning at the address specified by the user data start address register, until the next start code is detected. In this way, the CPU extracts the user data.
The MPEG decoder according to the present invention allows the CPU to read user data from the MPEG decoder regardless of the speed at which the CPU reads data.
An A/V separator, included in the MPEG decoder according to the present invention, has a user data detector which, upon detection of user data in entered code data, immediately outputs the user data detection signal to the CPU, with no decoding delay introduced by a video decoder, so that the CPU can start extracting the user data immediately. Therefore, even when the CPU is slower than the speed at which code data is stored into the memory, the CPU can extract user data before the memory containing the user data is updated by the next code data. This means that the CPU can extract user data regardless of the speed at which the CPU reads the user data.
Thus, the present invention eliminates the need to consider the speed at which the CPU reads user data from the MPEG decoder and therefore eliminates the need to increase the speed at which data is output from the MPEG decoder to the CPU. This results in a smaller LSI or eliminates the need for the MPEG decoder to be specifically designed for the speed of the CPU, thus lowering the development cost.